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STA240
Sirius SDARS channel, service & source decoder
Data Brief
Features

2 Satellite and 1 terrestrial signal demodulators and decoders Advanced DSP processor to implement PAC audio decoder Requires a single 17MHz clock reference; all high-speed clock signals are derived using on-chip PLL Programmable I2S to support 32K/48K/44.1K audio sample rate (32K/48K Sample rates use internal clocks, 44.1K Sample rate uses external clock) I2C master interface to control tuner and audio DAC External control through uart interface using sirius standard protocol (SSP) over RS-232
LBGA288

Description
STA240 is a fully integrated 3rd generation Baseband signal processor for Sirius Satellite Digital Radio Service (SDARS). It is implemented using ST Micro's advanced 0.13m HCMOS9 technology. It allows a highly efficient implementation of a Sirius "SDARS Satellite Digital Audio Radio Service" receiver when used with its companion STA210 tuner ASIC. STA240 is packaged in a low profile BGA (LBGA 19x19)
Analog to digital converters
Three internal 10 BIT A/D converters for 76.5MHZ if signals conversion
Low power technology

1.2V, 0.13 m technology 3.3V capable I/OS
Table 1.
Device summary
Part Number STA240 Package LBGA288 Packing Tray
June 2007
Rev 1
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www.st.com 6
For further information contact your local STMicroelectronics sales office.
Application block diagram
STA240
1
Application block diagram
Figure 1. Application block diagram
FLASH 1M x 16
STA210N Tuner FE
IF I2C IFAGC
STA240 STA240 Baseband Baseband Processor Processor
Audio/I 2S
Data
SDRAM 8Mbx8 or 16Mx8
AC00142
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STA240
Electrical specifications
2
2.1
Electrical specifications
Absolute maximum ratings
Table 2.
Symbol VDD VDDIO AD_VDD AD_VDD3 APLL_VDD Vi Vo Tstg Top Tj
Absolute maximum ratings
Parameter 1.2V Power supply voltage 3.3V Power supply voltage 1.2V Power supply voltage 3.3V Power supply voltage 1.2V Power supply voltage Voltage on input pin Voltage on output pin Storage temperature Operative ambient temperature Operative junction temperature Value -0.5 to 2 -0.5 to 4 -0.5 to 2 -0.5 to 4 -0.5 to 2 -0.5 to (VDDIO + 0.5) -0.5 to (VDDIO + 0.5) -55 to +150 -40 to +85 -40 to +125 Unit V V V V V V V C C C
2.2
Thermal data
Table 3.
Symbol Rth j-case Rth j-amb
Thermal Data
Parameter Thermal resistance junction to case Thermal resistance junction to ambient (1) Value 10 31 Unit C/W C/W
1. According to JEDEC specification on a 4 layers board
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Package information
STA240
3
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 2. LBGA 288 mechanical data & package dimensions
mm Ref. MIN. A A1 A2 A3 A4 b D D1 e E E1 F ddd eee fff 0.450 0.500 0.270 1.085 0.300 0.800 TYP. MAX. 1.700 0.0106 0.0427 0.0118 0.0315 MIN. TYP. MAX. 0.0669 inch
OUTLINE AND MECHANICAL DATA
0.550 0.0177 0.0197 0.0217
18.800 19.000 19.200 0.7402 0.7480 0.7559 17.000 1.000 0.6693 0.0394
18.800 19.000 19.200 0.7402 0.7480 0.7559 17.000 1.000 0.200 0.250 0.100 0.6693 0.0394 0.0079 0.0098 0.0039
LBGA288 (19x19x1.70) Low Profile Ball Grid Array
Bottom view
7131786 C
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STA240
Revision history
4
Revision history
Table 4.
Date 18-Jun-2007
Document revision history
Revision 1 Initial release. Changes
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STA240
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